(1) Field of the Invention
The present invention relates to the field of semiconductor fabrication. More specifically, the present invention relates to integrated circuits with structures that reduce or prevent damages to the integrated circuit.
(2) Background Information
Presently, semiconductor integrated circuits are manufactured by deposition and etch of a number of layers upon a silicon (Si) wafer. Device regions are formed within the Si wafer and then layers of conductive and non conductive material are formed over the device regions. These layers are then masked and etched to form semiconductor devices which are then connected by the use of conductive layers. The conductive layers typically include metal layers which are deposited, masked and etched to form interconnects. Subsequent layers are formed so as to define additional devices and interconnects. A top dielectric layer (hereinafter referred to as "passivation layer") is typically deposited over a top metal layer (hereinafter referred to as "terminal metal layer" or "TML") to planarize, insulate, prevent moisture penetration, thin film cracking, and other types of mechanical and chemical damages which may occur during assembly, packaging and operation of the individual integrated circuit die on the wafer.
FIG. 1 shows a cross-sectional view through a semiconductor wafer 100. Semiconductor wafer 100 includes a silicon substrate 101 that has several dielectric layers 102, 103 and 104 formed thereupon by processes that are well-known in the art. The figure also shows three metal layers that have been deposited, masked, and etched to form metal layers 105, 106, and 107. Metal layers 105-107 overlie device regions to connect the various devices and the subsequently deposited metal layers. A top dielectric layer 111 (passivation layer) is then formed over the terminal metal layer 105 to planarize, insulate the electrical devices and interconnects, to prevent leakage of electrical current through this passivation layer, etc. The passivation layer 111 may include a hard passivation layer 113 typically made of silicon nitride (SiN) and a soft passivation layer typically made of polyamide 115. The polyamide layer covers the silicon nitride layer. The soft passivation layer is deposited by Plasma Enhanced Chemical Vapor Deposition or other typically known passivation layer deposition processes. The layer of silicon nitride is then covered by polyamide or another type of soft passivation layer.
FIG. 2(a) illustrates a cross-section through the semiconductor wafer of FIG. 1 where the soft passivation layer 115 is partly delaminated from the hard passivation layer 113. The delamination typically allows moisture and other impurities to penetrate in the semiconductor wafer. One reason for the passivation layer's delamination is that the die is assembled into a plastic package which is more conducive to propagation of external forces within the package and to the die. The passivation layer, may also delaminate, when the die and the passivation layer are subjected to pressure pot testing (steam at a pressure greater than atmospheric pressure). One theory explaining this type of delamination is that steam dissolves or weakens the bonds within the passivation layer causing the passivation layer itself to delaminate.
Delamination is more likely to occur at the interface between the passivation layer 111 and the terminal metal layer 105. Delamination typically starts at the edge of the die and propagates towards the center of the die. If the delamination reaches an electrical interconnect, the forces within the die, that cause the delamination, are applied to the electrical interconnect causing the electrical interconnect to rip apart at weak points thereof.
FIG. 2(b) illustrates another cross section of the semiconductor wafer of FIG. 1 where the polyamide layer 115 delaminates together with the silicon nitride layer 113.
FIG. 2(c) illustrates a cross section of the semiconductor wafer of FIG. 1 where the terminal metal layer 105 and the passivation layer 111, including the silicon nitride layer 113 and the polyamide layer 115, delaminate from dielectric layer 104 as a result of external forces applied to the semiconductor wafer of FIG. 1.
What is needed is to provide a silicon wafer with reduced delamination of the passivation layer from the terminal metal layer, reduced delamination of the terminal metal layer and the passivation layer from a dielectric layer, and reduced delamination of the soft passivation layer from the hard passivation layer.
FIG. 3 illustrates a cross sectional view of a semiconductor wafer that has two chips 302 and 304 formed therein. These chips are separated by a sawing process. The sawing process, in this example, cuts the silicon substrate and all of the overlying layers to form the two chips 302 and 304.
FIG. 4 illustrates a top view of four dies 410 of a wafer separated therebetween by cuts resulting from a sawing process. Each die 410 has an active area 401 demarcated by dotted edge 421. Each die also includes, at a periphery thereof, a guard ring 412 surrounding the die area. Modern silicon wafers are typically provided, for each die, with a guard ring or guard wall that surrounds a die active area and that protects the die active area from damages. The damages include invasion by foreign impurities, such as sodium and magnesium that are existent in the environment, certain mechanical damages, including microcracks, produced by the wafer saw process and that propagate into an active die area of the chip, etc.
Saw cuts through the silicon wafer are typically not straight but rather wavy as shown in the figure (vertical cut 411 and horizontal cut 413). Also, the space between the dies through which the cut is made, is relatively small to provide more chips per wafer. Therefore, often, the saw cut may be made partially through the guard ring 412 as shown in the figure at 408 and 409. Cuts through the guard ring may cause failure of the guard ring to adequately protect the die active area and damages to the die active area 401 may ensue. Moreover, saw damage combined with reliability testing, (steam, temperature cycling, etc.) tend to cause the multi-layer structures of the silicon wafer to delaminate. It is desirable to provide a wafer that reduces the possibility of sawing cuts through the guard wall. It is also desirable to provide a way of preventing interlayer delamination.